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8.3.3
Write Command
( CS = "L", RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column
Address)
The WRITE command is used to initiate a burst write access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A8 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the WRITE burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
8.3.4
Burst Read with Auto-precharge Command
( CS = "L", RAS = "H", CAS ="L", WE = "H", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column
Address)
If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged.
The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles
later than the read with AP command if t RAS( min) and t RTP (min) are satisfied.
8.3.5
Burst Write with Auto-precharge Command
( CS = "L", RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column
Address)
If A10 is HIGH when a Write Command is issued, the Write with Auto-precharge function is engaged.
The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write
plus write recovery time (WR) programmed in the mode register.
8.3.6
Precharge All Command
( CS = "L", RAS = "L", CAS = "H", WE = "L" , BA0, BA1 = Don?t Care, A10 = "H", A0 to A9 and
A11 to A12 = Don?t Care)
The Precharge All command precharge all banks simultaneously. Then all banks are switched to the
idle state.
8.3.7
Self Refresh Entry Command
( CS = "L", RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Don ? t Care)
The Self Refresh command can be used to retain data, even if the rest of the system is powered
down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The
DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. ODT must be
turned off before issuing Self Refresh command, by either driving ODT pin LOW or using an EMRS
command. Once the command is registered, CKE must be held LOW to keep the device in Self
Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically
enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode, all of the
external signals except CKE, are “ Do n?t Care”.
The clock is internally disabled during self refresh operation to save power. The user may change the
external clock frequency or halt the external clock one clock after Self Refresh entry is registered;
however, the clock must be restarted and stable before the device can exit self refresh operation.
Publication Release Date: Sep. 03, 2012
- 21 -
Revision A03
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